ICS671-15 buffer equivalent, low skew buffer.
* Packaged in 24-pin TSSOP
* Input-output delay (±300 ps)
* Two ZDB 66 MHz outputs from a 66 MHz input AGP
clock
* Two ZDB 66 MHz outputs, plus four 33 M.
The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques. The ICS671-15 includes a Z.
The ICS671-15 is a low-jitter, low-skew, high-performance zero delay buffer (ZDB) for high-speed applications. The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques. The ICS671-15 includes a ZDB bank of four outp.
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